This invention is generally in the field of digital computers. In particular it is in the field of timing circuits for digital computers.
It is frequently necessary in digital computers to generate many timing signals, each having a different frequency, from a single fixed frequency clock signal. These timing signals are used to control various asynchronous tasks and processes within the computer.
A known circuit for generating a timing signal from a fixed frequency clock signal is shown in FIG. 1. A preload value is stored in preload register 125. At the start of operations, the preload value is moved through MUX 123 into decrementing counter 121. With each clock pulse, the value in counter 121 is decremented. If the value in the counter is zero or greater, it is reloaded into the counter through MUX 123 after the decrementing operation. When the value drops below zero, an underflow condition occurs, generating an underflow pulse from counter 121. This pulse also signals MUX 123 to reload the preload value in preload register 125 into counter 121. The generated rate is the number of times per second that the underflow pulse is generated.
For example, if counter 121 is clocked at 100 MHz and the value stored in register 125 is 99, counter 121 underflows at a 1 MHz rate. If the value in register 125 is changed to 19, counter 121 underflows at the rate of 5 MHz.
To generate a different rate, a new preload value must be placed in preload register 125. This is accomplished by placing the new value on a data line into the register and asserting a load command on a load signal line into the register.
This circuit has several deficiencies. Although the circuit is programmable, it can only generate a single rate at any given time. A new rate requires a new preload value which must be loaded into the preload register. If several timing signals are needed, an extra counter and preload register are needed for each separate rate. If many rates are needed, this solution becomes very expensive.
Small changes in the preload value can result in a large change in the underflow rate. In the last example, changing the value from 19 to 18 results in an timing signal of 5.263 MHz. Unless the counter frequency is changed, no frequency between 5 MHz and 5.263 MHz can be generated. As the underflow frequency goes up, this "resolution" worsens. Acceptable resolution using this circuit requires a very high frequency counter, much higher than the fastest rate that the user may want to generate. In turn, the preload register must be large to accommodate large preload values to generate lower frequency timing signals.
A rate generator that can be programmed to generate many different timing signals from a single clock signal with high resolution and low cost would be an improvement on known timing signal generators.